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irmck182m 1 www.irf.com ? 20 14 international rectifier submit datasheet feedback may 28, 2014 high performance sensorless motor control ic description irmck182m is a high performance one time programmable rom based motion control ic designed primarily for appliance applications which contains two computation engines integrated into one monolithic chip. one is the flexible motion control engine (mce tm ) for sensorl ess control of permanent magnet motors or induction motors; the other is an 8 - bit high - speed microcontroller (8051). the user can program a motion control algorithm by connecting these control elements using a graphic compiler. key components of the comple x sensorless control algorithms, such as the angle estimator, are provided as complete pre - defined control blocks. a unique analog/digital circuit and algorithm fully supports single shunt or leg shunt current reconstruction. irmck182m comes in a 32 pin qf n 5x5 package. features ? mce tm (flexible motion control engine) - dedicated computation engine for high efficiency sinusoidal sensorless motor control ? built - in hardware peripheral for single or two shunt current feedback reconstruction and analog circuits ? embedded 8 - bit high speed microcontroller (8051) for flexible i/o and man - machine control ? jtag programming port for e mulation/debugger ? serial communication interface (uart) ? watchdog timer with independent internal clock ? internal 32kbyte otp rom ? 3.3v single supply product summary maximum clock input (fcrystal) 60 mhz maximum internal clock (sysclk) 128mhz maximum 8051 clock (8051clk) 32mhz mce tm computation data range 16 bit signed 8051 /mce data ram 2kb mce program ram 12kb pwm carrier frequency 20 bits/ sysclk a/d input channels 4 a/d converter resolution 12 bits a/d converter co nversion speed 2 sec analog output (pwm) resolution 8 bits uart baud rate (typ) 57.6 k bps number of digital i/o (max) 7 package (lead free) qfn32 maximum 3.3v operating current 60ma base part number package type standard pack orderable part number form quantity irmck182m qfn32 tape and reel 3000 irmck182mtr tray 3120 irmck182mty
irmck182 2 www.irf.com ? 2014 international rectifier submit datasheet feedback may 28, 2014 table of content s 1 overview .................................................................................................................................... 5 2 pinout ......................................................................................................................................... 6 3 irmck182m block di agram and main functions ...................................................................... 7 4 application connection and pin function .................................................................................... 9 4.1 8051 peripheral interface group ....................................................................................... 10 4.2 motion peripheral interface group .................................................................................... 11 4.3 analog interface group ..................................................................................................... 11 4.4 power interface group ...................................................................................................... 11 4.5 test interface group ......................................................................................................... 11 5 dc characteristics ................................................................................................................... 13 5.1 absolute maximum ratings ............................................................................................... 13 5.2 system clock frequency and power consumption .......................................................... 13 5.3 digital i/o dc characteristics ............................................................................................ 14 5.4 analog i/o (ifbu+,ifbu - ,ifbuo, ifbv+,ifbv - ,ifbvo) dc characteristics .................... 15 5.5 under voltage lockout dc characteristics ........................................................................ 16 5.6 itrip comparator dc characteristics ................................................................................... 16 6 ac characteristics ................................................................................................................... 17 6.1 digital pll ac characteristics .......................................................................................... 17 6.2 analog to digital converter ac characteristics ................................................................. 18 6.3 op amp ac characteristics ............................................................................................... 19 6.4 sync to svpwm and a/d conversion ac timing ........................................................... 20 6.5 gatekill to svpwm ac timing ..................................................................................... 21 6.6 itrip ac timing ................................................................................................................... 21 6.7 uart ac timing ............................................................................................................... 21 6.8 capture input ac timing .............................................................................................. 23 6.9 otp programming timing ................................................................................................. 24 6.10 jtag ac timing ............................................................................................................... 25 7 i/o structure ............................................................................................................................. 26 8 pin list ..................................................................................................................................... 29 9 package dimensio ns ............................................................................................................... 31 10 part marking information .......................................................................................................... 32 11 qualification information .......................................................................................................... 32
irmck182 3 www.irf.com ? 2014 international rectifier submit datasheet feedback may 28, 2014 list of tables table 1 absolute maximum ratings ......................................................................................................... 13 table 2 system clock frequency ............................................................................................................. 13 table 3 digital i/o dc characteristics ...................................................................................................... 14 table 5 analog i/o dc characteristics .................................................................................................... 15 table 6 uvcc dc characteristics .............................................................................................................. 16 table 7 itrip dc characteristics ................................................................................................................. 16 table 8 pll ac characteristics ................................................................................................................ 17 table 9 a/d converter ac characteristics .............................................................................................. 18 table 10 current sensing op amp ac characteristics ........................................................................ 19 table 11 sync ac characteristics .......................................................................................................... 20 table 12 gatekill to svpwm ac timing ............................................................................................ 21 table 13 itrip ac timing ............................................................................................................................. 21 tabl e 14 uart ac timing ......................................................................................................................... 22 table 15 capture ac timing ................................................................................................................. 23 table 16 otp programming timing ......................................................................................................... 24 table 17 jtag ac timing ......................................................................................................................... 25 table 18 pin list .......................................................................................................................................... 30
irmck182 4 www.irf.com ? 2014 international rectifier submit datasheet feedback may 28, 2014 list of figures figure 1 typical application block diagram using irmck182m ..................................................... 5 figure 2 pinout of irmck182m ........................................................................................................ 6 figure 3 crystal circuit example ..................................................................................................... 17 figure 4 voltage droop and s/h hold time ..................................................................................... 18 figure 5 a capacitor of 47pf is recommended at the output pin of all op amps. ........................... 19 figure 6 sync timing ..................................................................................................................... 20 figure 7 gatekill timing ................................................................................................................... 21 figure 8 itrip timing ..................................................................................................................... 21 figure 9 uart timing ..................................................................................................................... 22 figure 10 capture timing ............................................................................................................ 23 figure 11 otp programming timing ............................................................................................... 24 figure 12 jtag timing ................................................................................................................... 25 figure 13 pwmul/pwmuh/pwmvl/pwmvh/pwmwl/pwmwh output .................................... 26 figure 14 all digital i/o except motor pwm output ......................................................................... 26 figure 15 reset, gatekill i/o .................................................................................................. 27 figure 16 analog input ................................................................................................................... 27 figure 17 analog operational amplifier output and aref i/o structure ......................................... 27 figure 18 vpp programming pin i/o structure ............................................................................... 28 figure 19 vss and avss pin structure .......................................................................................... 28 figure 20 vdd1 and vddcap pin structure .................................................................................. 28 figure 21 xtal0/xtal1 pins structure .......................................................................................... 28
irmck182 5 www.irf.com ? 2014 international rectifier submit datasheet feedback may 28, 2014 1 overview irmck182m is a new generation international rectifier integrated circuit device primarily designed as a one- chip solution for complete inverter controlled appliance motor control applications. unlike a traditional microcontroller or dsp, the irmck182m provides a bu ilt - in closed loop sensorless control algorithm using the unique f lexible motion control engine ( mce tm ) for permanent magnet motors as well as induction motors . the mce tm consists of a collection of control elements, motion peripherals; a dedicated motion control sequencer and dual port ram to map internal signal nodes. irmck182m also employs a unique single shunt current reconstruction circuit in addition to two leg shunt current sensing circuit to eliminate additional analog/digital circuitry and enables a direct shunt resistor interface to the ic. motion control programming is achieved using a dedicated graphical compiler integrated into the matlab/simulink tm development environment. sequencing, user interface, host communication, and upper layer contro l tasks can be implemented in the 8051 high - speed 8 - bit microcontroller. the 8051 microcontroller is equipped with a jtag port to facilitate emulation and debugging tools. figure 1 shows a typical application schematic using the irmck182m . irmck182m contains 32k bytes of otp program rom, and come s in a 32- pin qfn package. irmck182 power supply irs2336d pm motor ipm or spm or im motor passive emi fillter digital i/o analog input host communication (rs232c) appliance pm motor drive 3.3v gate signal 15v 4 7 galvanic isolation figure 1 typical application block diagram using irmck182m
irmck182 6 www.irf.com ? 2014 international rectifier submit datasheet feedback may 28, 2014 2 pinout pin out shown is based on qfn 5 x 5 32 pin package. 3 3 4 4 5 5 6 6 7 7 8 8 2 2 1 1 vss vss tck tck tdi / p 5 . 1 tdi / p 5 . 1 vdd 1 vdd 1 xtal 1 xtal 1 vddcap vddcap reset reset p 1 . 1 / rxd p 1 . 1 / rxd xtal 0 xtal 0 vss vss vdd 1 vdd 1 vddcap vddcap pwmvh pwmvh pwmul pwmul pwmvl pwmvl ifbv - ifbv - ifbuo ifbuo ifbu + ifbu + pwmuh pwmuh tdo / p 5 . 3 tdo / p 5 . 3 tms / p 5 . 2 tms / p 5 . 2 mck 182 mck 182 ( top view ) ( top view ) ain 1 ain 1 ifbv + ifbv + p 1 . 2 / txd p 1 . 2 / txd vpp / gatekill vpp / gatekill ifbu - ifbu - ain 0 ain 0 p 2 . 6 / aopwm 0 p 2 . 6 / aopwm 0 avss avss pwmwl pwmwl 13 13 14 14 15 15 16 16 11 11 10 10 12 12 9 9 18 18 19 19 20 20 21 21 22 22 23 23 24 24 17 17 25 25 26 26 32 32 31 31 30 30 29 29 28 28 27 27 pwmwh pwmwh ifbvo ifbvo figure 2 pinout of irmck182m
irmck182 7 www.irf.com ? 2014 international rectifier submit datasheet feedback may 28, 2014 3 irmck182m block diagram and main functions irmck182m block diagram is shown in figure 3 . motion control sequencer dual port ram 2kbyte mce program ram 12kbyte program rom/ram 32kb 8bit up address/data bus motion control bus a/d mux s/h d/a (pwm) timer counnter0,1,2 watchdog timer motion control modules uart snd rcv 6 low loss svpwm gatekill to igbt gate drive mini -motion control engine (mini mce) monitoring host interface digital i/os 8bit (8051 ) microcontroller jtag emulator debugger 4 freq synthesizer 2 ceramic resonator (4mhz) 32mhz analog input 2 capture interrupt control single shunt motor current reconstruction from shunt resistor speed command port 1 port 2 port 5 8bit cpu core local ram 2kbyte 128mhz ain0 ain1 ifbu 3 ifbv 3 figure 3 irmck182m block diagram irmck182m contains the following functions for sensorless ac motor control applications: ? motion control engine (mce tm ) o sensorless foc (complete sensorless field oriented control) o proportional plus integral block o low pass filter o differentiator and lag (high pass filter) o ramp o limit o angle estimate (sensorless control) o inverse clark transformation o vector rotator o bit latch o peak detect
irmck182 8 www.irf.com ? 2014 international rectifier submit datasheet feedback may 28, 2014 o transition o multiply - divide (signed and unsigned) o divide (signed and unsigned) o adder o subtractor o comparator o counter o accumulator o switch o sh ift o atan (arc tangent) o function block (any curve fitting, nonlinear function) o 16 bit wide logic operations (and, or, xor, not, negate) o mce tm program memory and dual port ram (max 12k+2k byte) o mce tm control sequencer ? 8051 microcontroller o two 16 bit timer/counters o one 16 bit periodic timer o one 16 bit watchdog timer o one 16 bit capture timer o up to 7 discrete i/os o 4 channel 12 bit a/d ? buffered (current sensing) two channel s (0 ? 1.2v input) ? unbuffered two channels (0 ? 1.2v input) o jtag port (4 pins) o up t o three channels of analog output (8 bit pwm) o uart o 32k byte otp program rom o 2k byte data ram
irmck182 9 www.irf.com ? 2014 international rectifier submit datasheet feedback may 28, 2014 4 application connection and pin function p1. 2/txd p1.1 /rxd xtal0 pwmuh pwmul pwmvh pwmvl pwmwh pwmwl gatekill ain0, ain1 host microcontroller (rs232c ) digital i/o control system clock 4mhz crystal analog output xtal1 tdi/p 5.1 reset p5. 1/t di jtag control (otp programming & emulation) tclk p5.2/tms tdo avref ifbu+ ifbu- ifbuo other analog input (0-1. 2v) avdd 1.8v avss vdd1 3.3 v vss ifbv+ ifbv- ifbvo optional external voltage reference (0.6v) frequency synthesizer rs232c port1 port2 reset pwm1 jtag interface low loss space vector pwm s/h s/h 8051 cpu dual port memory (2kb) & mce memory (12kb) motion control modules motion control sequencer 12bit a/d & mux system clock local ram (2kbyte) program ram (32kbyte) system reset watchdog timer timers irmck182 port5 p1.5/vpp /gk tdo/p5. 3 4 1.8v voltage regulator vddcap 3.3v tms/p5.2 otp programming voltage (6.5v) motor hvic gate drive irs2336d avref single shunt current sensing p1. 2/txd p1.1/rxd p2. 6/aopwm 0 p2. 7/aopwm 1 p2. 6/aopwm 0 p1. 5 figure 4 irmck182m connection diagram
irmck182 10 www.irf.com ? 2014 international rectifier submit datasheet feedback may 28, 2014 4.1 8051 peripheral interface group uart interface p1.2/txd output, transmit data from irmck182m p1.1/rxd input, receive data to irmck182m discrete i/o interface p1.1/rxd input/output port 1.1, can be configured as rxd input p1.2/txd input/output port 1.2, can be configured as txd output vpp /gk otp programming voltage , or gatekill input p2. 6 /aopwm 0 input/output port 2. 6 , can be configured as aopwm 0 output p2.7/aopwm1 input/output port 2.7, can be configured as aopwm1 output p5.1/tdi input port 5.1, configured as jtag port by default p5.2/tms input port 5.2, configured as jtag port by default analog output interface p2. 6 /aopwm 0 input/output, can be configured as 8 - bit pwm output 0 with programmable carrier frequency p2.7/aopwm1 input/output, can be configured as 8 - bit pwm output 1 with program mable carrier frequency crystal interface xtal0 input, connected to crystal xtal1 output, connected to crystal reset interface reset input and output, system reset, doesn?t require external rc time constant
irmck182 11 www.irf.com ? 2014 international rectifier submit datasheet feedback may 28, 2014 4.2 motion peripheral interface group pwm pwmuh output, pwm phase u high side gate signal, internally pulled down by 58k? pwmul output, pwm phase u low side gate signal, internally pulled down by 58k? pwmvh output, pwm phase v high side gate signal, internally pulled down by 58k? pwmvl output, pwm phase v low side gate signal, internally pulled down by 58k? pwmwh output, pwm phase w high side gate signal, internally pulled down by 58k? pwmwl output, pwm phase w low side gate signal, internally pulled down by 58k? fault gatekill input, upon assertion, th is negates all six pwm signals, active low, internally pulled up by 70k? 4.3 analog interface group avss analog power return, (analog internal 1.8v power is shared with vddcap) ifb u + input, operational amplifier positive input for single or u - phase leg shunt resistor current sensing ifb u - input, operational amplifier negative input for single or u - phase leg shunt shunt resistor current sensing ifb u o output, operational amplifier output for single or u - phase leg shunt shunt resistor current sensing ifb v + input , operational amplifier positive input for v - phase leg shunt resistor current sensing ifb v - input, operational amplifier negative input for v - phase leg shunt shunt resistor current sensing ifb v o output, operational amplifier output for v - phase leg shunt sh unt resistor current sensing ain0 input, analog input channel 0 (0 ? 1.2v), typically configured for dc bus voltage input ain1 input, analog input channel 1 (0 ? 1.2v), needs to be pulled down to avss if unused 4.4 power interface group vdd1 digital power (3.3v) vddcap internal 1.8v output, requires capacitors to the pin. shared with analog power pad internally note: the internal 1.8v supply is not designed to power any external circuits or devices. only capacitors should be connected to this pin. vss digital common 4.5 test interface group
irmck182 12 www.irf.com ? 2014 international rectifier submit datasheet feedback may 28, 2014 p5.2/tms jtag test mode input or input/output digital port tdo jtag data output p5.1/tdi jtag data input, or input/output digital port tck jtag test clock
irmck182 13 www.irf.com ? 2014 international rectifier submit datasheet feedback may 28, 2014 5 dc characteristics 5.1 absolute maximum ratings symbol parameter min typ max condition v dd1 supply voltage - 0.3 v - 3.6 v respect to vss v ia analog input voltage - 0.3 v - 1.98 v respect to avss v id digital input voltage - 0.3 v - 6.0 v respect to vss v pp otp programming voltage - 0.3v - 7.0v respect to vss t a ambient temperature - 40 ?c - 85 ?c t s storage temperature - 65 ?c - 150 ?c table 1 absolute maximum ratings caution: stresses beyond those listed in ?absolute maximum ratings? may cause permanent damage to the device. these are stress ratings only and function of the device at these or any other conditions beyond those indicated in the operational sections of the specif ications are not implied. 5.2 system clock frequency and power consumption c aref = 1nf, c mext = 100nf. vdd1=3.3v, unless specified, ta = 25?c. symbol parameter min typ max unit sysclk system clock 32 - 128 mhz p d power consumption 160 1) 200 mw table 2 system clock frequency note 1) the value is based on the condition of mce clock=126mhz, 8051 clock 31.5mhz with a actual motor running by a typical mce application program and 8051 code.
irmck182 14 www.irf.com ? 2014 international rectifier submit datasheet feedback may 28, 2014 5.3 digital i/o dc characteristics symbol parameter min typ max condition v dd1 supply voltage 3.0 v 3.3 v 3.6 v recommended v pp otp programming voltage 6.70v 6.75v 6.80v recommended v il input low voltage - 0.3 v - 0.8 v recommended v ih input high voltage 2.0 v 3.6 v recommended c in input capacitance - 3.6 pf - (1) i l input leakage current 10 na 1 a v o = 3.3 v or 0 v i ol2 (2) low level output current 17.9 ma 26.3 ma 33.4 ma v ol = 0.4 v (1) i oh2 (2) high level output current 24.6 ma 49.5 ma 81 ma v oh = 2.4 v (1) table 3 digital i/o dc characteristics note: (1) data guaranteed by design. (2) applied to all digital i/o pins.
irmck182 15 www.irf.com ? 2014 international rectifier submit datasheet feedback may 28, 2014 5.4 analog i/o (ifb u +,ifb u - ,ifb u o, ifb v +,ifb v - ,ifb v o ) dc characteristics c aref = 1nf, c mext = 100nf. vdd1=3.3v, unless specified, ta = 25?c. symbol parameter min typ max condition v offset input offset voltage - - 26 mv v i input voltage range 0 v 1.2 v recommended v outsw op amp output operating range 50 mv (1) - 1.2 v c in input capacitance - 3.6 pf - (1) r fdbk op amp feedback resistor 5 k ? - 20 k ? requested between ifbo and ifb - op gaincl operating close loop gain 80 db - - (1) cmrr common mode rejection ratio - 80 db - (1) i src op amp output source current - 1 ma - v out = 0.6 v (1) i snk op amp output sink current - 100 a - v out = 0.6 v (1) table 4 analog i/o dc characteristics note: (1) data guaranteed by design.
irmck182 16 www.irf.com ? 2014 international rectifier submit datasheet feedback may 28, 2014 5.5 under voltage lockout dc characteristics unless specified, ta = 25?c. symbol parameter min typ max condition uv cc+ uvcc positive going threshold 2.78 v 3.04 v 3.23 v (1) uv cc- uvcc negative going threshold 2.78 v 2.97 v 3.23 v uv cc h uvcc hysteresys - 73 mv - (1) table 5 uvcc dc characteristics note: (1) data guaranteed by design. 5.6 itrip comparator dc characteristics unless specified, vdd1=3.3v, ta = 25?c. symbol parameter min typ max condition itrip + itrip positive going threshold - 1.22v - itrip - itrip negative going threshold - 1.10v - itriph itrip hysteresys - 120mv - table 6 itrip dc characteristics
irmck182 17 www.irf.com ? 2014 international rectifier submit datasheet feedback may 28, 2014 6 ac characteristics 6.1 digital pll ac characteristics symbol parameter min typ max condition f clkin crystal input frequency 3.2 mhz 4 mhz 60 mhz (1) (see figure below) f pll internal clock frequency 32 mhz 50 mhz 128 mhz (1) f lwpw sleep mode output frequency f clkin 256 - - (1) j s short time jitter - 200 psec - (1) d duty cycle - 50 % - (1) t lock pll lock time - - 500 sec (1) table 7 pll ac characteristics note: (1) data guaranteed by design. xtal r 1 =1m ? r 2 =1 k ? c 1 =30pf c 2 = 30pf figure 3 crystal circuit example
irmck182 18 www.irf.com ? 2014 international rectifier submit datasheet feedback may 28, 2014 6.2 analog to digital converter ac characteristics unless specified, ta = 25?c. symbol parameter min typ max condition t conv conversion time - - 2.05 sec (1) t hold sample/hold maximum hold time - - 10 sec voltage droop 15 lsb (see figure below) table 8 a/d converter ac characteristics note: (1) data guaranteed by design. t h o l d v o l t a g e d r o o p t sampl e s / h v o l t a g e i n p u t v o l t a g e figure 4 voltage droop and s/h hold time
irmck182 19 www.irf.com ? 2014 international rectifier submit datasheet feedback may 28, 2014 6.3 op amp ac characteristics unless specified, ta = 25?c. symbol parameter min typ max condition op sr op amp slew rate - 10 v/sec - vdd1 = 3.3 v, cl = 33 pf (1) op imp op input impedance - 10 8 - (1) (2) t set settling time - 400 ns - vdd1 = 3.3 v, cl = 33 pf (1) table 9 current sensing op amp ac characteristics note: (1) data guaranteed by design. (2) to guarantee stability of the operational amplifier, it is recommended to load the output pin by a capacitor of 47pf, see figure 5 . here only the single shunt current amplifier is show but all op amp outputs should be loaded with this capacitor. avref ifbc + ifbc - ifbco irmck 172 ic external components 47 pf figure 5 a capacitor of 47pf is recommended at the output pin of all op amps.
irmck182 20 www.irf.com ? 2014 international rectifier submit datasheet feedback may 28, 2014 6.4 sync to svpwm and a/d conversion ac t iming sync iu , iv , iw t w sync t dsync 1 ainx t dsync 2 pwmux , pwmvx , pwmwx t dsync 3 figure 6 sync timing unless specified, ta = 25?c. symbol parameter min typ max unit t wsync sync pulse width - 32 - sysclk t dsync1 sync to current feedback conversion time - - 100 sysclk t dsync2 sync to ain0 - 5 analog input conversion time - - 200 sysclk (1) t dsync3 sync to pwm output delay time - - 2 sysclk table 10 sync ac characteristics note: (1) ain1 through ain5 channels are converted once every 6 sync events
irmck182 21 www.irf.com ? 2014 international rectifier submit datasheet feedback may 28, 2014 6.5 gatekill to svpwm ac t iming gatekill pwmux,pwmvx,pwmwx t wgk t dgk figure 7 gatekill timing unless specified, ta = 25?c. symbol parameter min typ max unit t wgk gatekill pulse width 32 - - sysclk t dgk gatekill to pwm output delay - - 100 sysclk table 11 gatekill to svpwm ac timing 6.6 itrip ac timing itrip pwmuh , pwmul , pwmvh , pwmvh , pwmwh , pwmwl t itrip figure 8 itrip timing unless specified, ta = 25?c. symbol parameter min typ max unit t itrip itrip propagation delay - - 100(sysclk)+1.0usec sysclk+usec table 12 itrip ac timing 6.7 uart ac timing
irmck182 22 www.irf.com ? 2014 international rectifier submit datasheet feedback may 28, 2014 txd rxd data and parity b it start bit t baud stop bit t uartfil figure 9 uart timing unless specified, ta = 25?c. symbol parameter min typ max unit t baud baud rate period - 57600 - bit/sec t uartfil uart sampling filter period (1) - 1/16 - t baud table 13 uart ac timing note: (1) each bit including start and stop bit is sampled three times at center of a bit at an interval of 1/16 t baud . if three sampled values do not agree, then uart noise error is generated.
irmck182 23 www.irf.com ? 2014 international rectifier submit datasheet feedback may 28, 2014 6.8 capture input ac timing capture pin crev(h,l) internal register t caphigh t capclk t crdelay t caplow t cldelay clast(h,l) internal register t intdelay interrupt vector fetch interrupt figure 10 capture timing unless specified, ta = 25?c. symbol parameter min typ max unit t capclk capture input period 8 - - sysclk t caphigh capture input high time 4 - - sysclk t caplow capture input low time 4 - - sysclk t crdelay capture falling edge to capture register latch time - - 4 sysclk t cldelay capture rising edge to capture register latch time - - 4 sysclk t intdelay capture input interrupt latency time - - 4 sysclk table 14 capture ac timing
irmck182 24 www.irf.com ? 2014 international rectifier submit datasheet feedback may 28, 2014 6.9 otp programming timing tck tdi/tms vpp t vps t vph 6.75v vdd/vss/floating vdd/vss/floating figure 11 otp programming timing unless specified, ta = 25?c. symbol parameter min typ max unit t vps vpp setup time 10 - - nsec t vph vpp hold time 15 - - nsec table 15 otp programming timing
irmck182 25 www.irf.com ? 2014 international rectifier submit datasheet feedback may 28, 2014 6.10 jtag ac timing tck tdo t jhigh t jclk t co t jlow t jsetup t jhold tdi / tms figure 12 jtag timing unless specified, ta = 25?c. symbol parameter min typ max unit t jclk tck period - - 50 mhz t jhigh tck high period 10 - - nsec t jlow tck low period 10 - - nsec t co tck to tdo propagation delay time 0 - 5 nsec t jsetup tdi/tms setup time 4 - - nsec t jhold tdi/tms hold time 0 - - nsec table 16 jtag ac timing
irmck182 26 www.irf.com ? 2014 international rectifier submit datasheet feedback may 28, 2014 7 i/o structure the following figure shows the motor pwm output (pwmuh/pwmul/pwmvh/pwmvl/pwmwh/pwmwl) 270 ? 6.0v 6.0v internal digital circuit high true logic vdd1 (3.3v ) vss 58k ? pin figure 13 pwmul/pwmuh/pwmvl/pwmvh/pwmwl/pwmwh output the following figure shows the digital i/o structure except the motor pwm output 6.0v 6.0v internal digital circuit low true logic vdd1 (3.3v) 70k ? pin vss 270 ? figure 14 all digital i/o except motor pwm output the following figure shows reset and gatekill i/o structure.
irmck182 27 www.irf.com ? 2014 international rectifier submit datasheet feedback may 28, 2014 270 ? 6 . 0 v 6 . 0 v reset gatekill circuit vdd 1 ( 3 . 3 v ) 70 k ? pin vss figure 15 reset, gatekill i/o the following figure shows the analog input structure. 1 ? 6.0v 6.0v analog input pin avss analog circuit vddcap(1.8v) figure 16 analog input the following figure shows all analog operational amplifier output pins and aref pin i/o structure. 6 . 0 v 6 . 0 v analog out put pin avss analog circuit vddcap ( 1 . 8 v ) figure 17 analog operational amplifier output and aref i/o structure
irmck182 28 www.irf.com ? 2014 international rectifier submit datasheet feedback may 28, 2014 the following figure shows the vpp pin structure pin vss 8.0v 270 ? figure 18 vpp programming pin i/o structure the following figure shows the vss and avss pins structure pin vdd 1 avdd 6 . 0 v figure 19 vss and avss pin structure the following figure shows the vdd1 and vddcap pin structure pin vss 6.0v figure 20 vdd1 and vddcap pin structure the following figure shows the xtal0 and xtal1 pins structure 1 ? 6.0v 6.0v pin vss vddcap(1.8v) figure 21 xtal0/xtal1 pins structur e
irmck182 29 www.irf.com ? 2014 international rectifier submit datasheet feedback may 28, 2014 8 pin list pin number pin name internal pull - up /pull - down pin type description 1 reset i/o reset, low true, schmitt trigger input 2 p1.1/rxd i/o uart receiver input or discrete programmable i/o 3 p1.2/t xd i/o uart transmitter output or discrete programmable i/o 4 xtal0 i crystal input 5 xtal1 o crystal output 6 vdd1 p 3.3v digital power 7 vss p digital common 8 vddcap p internal 1.8v output, capacitor(s) to be connected 9 p2.6/aopwm0 i/o discrete programmable i/o or pwm 0 digital output 10 ain0 i analog input channel 0, 0 - 1.2v range, needs to be pulled down to avss if unused 11 ain1 i analog input channel 1, 0 - 1.2v range, needs to be pulled down to avss if unused 12 ifbu - i single or u - phase leg shunt current sensing op amp input ( - ) 13 ifbu+ i single or u - phase leg shunt current sensing op amp input (+) 14 ifbuo o single or u - phase leg shunt current sensing op amp output 15 ifbv - i single or v - phase leg shunt current sensing op amp input ( - ) 16 ifbv+ i single or v - phase leg shunt current sensing op amp input (+) 17 ifbvo o single or v - phase leg shunt current sensing op amp output 18 avss p analog ground 19 vddcap p internal 1.8v output, capacitor(s) to be connected 20 vdd1 p 3.3v digital power 21 vss p digital common 22 pwmwl 58 k pull down o pwm gate drive for phase w low side, configurable either high or low true. 23 pwmvl 58 k pull down o pwm gate drive for phase v low side, configurable either high or low true 24 pwmul 58 k pull down o pwm gate drive for phase u low side, configurable either high or low true 25 pwmwh 58 k pull down o pwm gate drive for phase w high side, configurable either high or low true 26 pwmvh 58 k pull down o pwm gate drive for phase v high side, configurable either high or low true
irmck182 30 www.irf.com ? 2014 international rectifier submit datasheet feedback may 28, 2014 pin number pin name internal pull - up /pull - down pin type description 27 pwmuh 58 k pull down o pwm gate drive for phase u high side, configurable either high or low true 28 vpp/gk i/o p otp programming power (6.5v) and pwm shutdown input 29 tms/ p5.2 i/o jtag test mode select or discrete i/o 30 tdo /p5.3 o jtag test data output 31 tdi /p5.1 i/o jtag test data input or discrete i/o 32 tck i jtag test clock table 17 pin list
irmck182 31 www.irf.com ? 2014 international rectifier submit datasheet feedback may 28, 2014 9 package dimensions
irmck182 32 www.irf.com ? 2014 international rectifier submit datasheet feedback may 28, 2014 10 part marking information mck 182 ywwp xxxxxx ir logo production lot date code part number pin 1 indentifier 11 qualification information qu ali f ica t i on l e v el ?? industrial (per jedec jesd47) m o is tu r e se n si t i v i t y l e v el m s l 2 ??? ( per i p c/ j e d e c j - s t d - 020) esd m ach i n e m od el c l a s s b ( per j e d e c s ta n da r d j es d22 - a 115) h um an b od y m odel c l a s s 2 ( per ansi/esda/ j e d e c js - 001 ) charged device m odel class c2 ( per j e d e c s ta n da r d j es d22 - c101 ) latch - up class i, level b (per j e d e c s ta n da r d j es d78) r o hs c o m p l i a n t y es ? qualification standards can be found at international rectifier?s web site http://www.irf.com/ ?? higher qualification ratings may be available should the user have such requirements. please contact your international rect ifier sales representative for further information. ??? higher msl ratings may be available for the specific package types listed here. please contact your international rectifier sales representative for further information.
irmck182 33 www.irf.com ? 2014 international rectifier submit datasheet feedback may 28, 2014 data and specifications are subject to change without notice ir world headquarters: 233 kansas st., el segundo, california 90245, usa tel: (310) 252 - 7105 tac fax: (310) 252 - 7903 visit us at www.irf.com for sales contact information

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